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fn3093 rev.4.00 page 1 of 15 aug 28, 2007 fn3093 rev.4.00 aug 28, 2007 icl7135 4 1/2 digit, bcd output, a/d converter datasheet the intersil icl7135 precisi on a/d converter, with its multiplexed bcd out put and digit drive rs, combines dual- slope conversion reliability with ? 1 in 20,000 count accuracy and is ideally suited for the visual display dvm/dpm market. the 2.0000v full scale cap ability, auto-zero, and auto- polarity are combined with true ratiometric operation, almost ideal differential linearity a nd true differential input. all necessary active devices are contained on a single cmos lc, with the exception of displ ay drivers, reference, and a clock. the icl7135 brings together an unprecedented combination of high accuracy, versatility, a nd true economy. it features auto-zero to less than 10 ? v, zero drift of less than 1 ? v/ o c, input bias current of 10pa (ma x), and rollover error of less than one count. the versatility of multiplexed bcd outputs is increased by the addition of se veral pins which allow it to operate in more sophisticat ed systems. these include strobe , overrange, unde rrange, run/hold and busy lines, making it possible to interface the circuit to a microprocessor or uart. features ? accuracy guaranteed to ? 1 count over entire ?? 20000 counts (2.0000v full scale) ? guaranteed zero reading for 0v input ? 1pa typical input leakage current ? true differential input ? true polarity at zero count f or precise null detection ? single reference voltage required ? overrange and underrange signals available for auto- range capability ? all outputs ttl compatible ? blinking outputs gives visu al indication of overrange ? six auxiliary inputs/outputs are available for interfacing to uarts, microprocessors, or other circuitry ? multiplexed bcd outputs ? pb-free plus anneal available (rohs compliant) pinout icl7135 (pdip) top view ordering information part number part marking temp. range (c) package pkg. dwg. # ICL7135CPI ICL7135CPI 0 to +70 28 ld pdip e28.6 ICL7135CPIz (note 1) ICL7135CPIz 0 to +70 28 ld pdip (pb-free) (note 2) e28.6 notes: 1. intersil pb-free plus anneal pr oducts employ special pb-free material sets; molding com pounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 2. pb-free pdips can be used for through hole wave solder processing only. they are not i ntended for use in reflow solder processing applications. v- reference nalog common int out az in buff out ref cap - ref cap + in lo in hi v+ (msd) d5 (lsb) b1 b2 underrange strobe r/h digital gnd pol busy d2 d3 d4 (msb) b8 b4 overrange clock in (lsd) d1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14
icl7135 fn3093 rev.4.00 page 2 of 15 aug 28, 2007 typical application schematic 28 27 26 25 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 24 set v ref = 1.000v v ref in signal -5v +5v 100k ? 27 ? 100k ? 100k analog gnd input 1 ? f 0.47 ? f 1 ? f 0.1 ? f 100k ? icl7135 clock in 120khz 0v 6 anode driver transistors seven seg. decode display
icl7135 fn3093 rev.4.00 page 3 of 15 aug 28, 2007 absolute maximum ratings thermal information supply voltage v+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6v v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -9v analog input voltage (either input) (note 1) . . . . . . . . . . . . v+ to v- reference input voltage (either input). . . . . . . . . . . . . . . . . v+ to v- clock input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd to v+ operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to +70 o c thermal resistance (typical, note 2) . . . . . . . . . . . . . ? ja ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . .+150 o c maximum storage temperature range . . . . . . . . . -65 o c to +150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . .+300 o c note: pb-free pdips can be used for through hole wave solder processing only. they are not intended for use in reflow solder processing applications. caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. input voltages may exceed the supply voltages provided the in put current is limited to +100 ? a. 2. ? ja is measured with the component mounted on a low effective ther mal conductivity test board in fr ee air. see tech brief tb379 f or details. electrical specifications v+ = +5v, v- = -5v, t a = +25 o c, f clk set for 3 readings/s, unless otherwise specified parameter test conditions min typ max units analog (notes 3, 4) zero input reading v ln = 0v, v ref = 1.000v -00000 +00000 +00000 counts ratiometric error (note 4) v ln = v ref = 1.000v -3 0 +3 counts linearity over ? full scale (error of reading from best straight line) -2v ? v in ? +2v - 0.5 1 lsb differential linearity (difference between worse case step of adjacent counts and ideal step) -2v ? v in ? +2v - 0.01 - lsb rollover error (difference in r eading for equal positive and negative voltage near full scale) -v ln ?? +v ln ? 2v - 0.5 1 lsb noise (peak-to-peak value not exceeded 95% of time), e n v ln = 0v, full scale = 2.000v - 15 - ? v input leakage current, i ilk v ln = 0v - 1 10 pa zero reading drift (note 7) v ln = 0v, 0 o c to +70 o c-0.52 ? v/ o c scale factor temperature coefficient, t c (notes 5 and 7) v ln = +2v, 0 o c to +70 o c ext. ref. 0ppm/ o c - 2 5 ppm/ o c digital inputs clock in, run/hold (see figure 2) v inh 2.8 2.2 - v v inl -1.60.8 v i inl v in = 0v - 0.02 0.1 ma i inh v in = +5v - 0.1 10 ? a digital outputs all outputs, v ol i ol = 1.6ma - 0.25 0.40 v b1, b2, b4, b8, d1, d2, d3, d4, d5, v oh i oh = -1ma 2.4 4.2 - v busy, strobe , overrange, underra nge, polarity, v oh i oh = -10 ? a 4.9 4.99 - v supply +5v supply range, v+ +4 +5 +6 v -5v supply range, v- -3 -5 -8 v +5v supply current, i+ f c = 0 - 1.1 3.0 ma -5v supply current, i- f c = 0 - 0.8 3.0 ma power dissipation capacitance, c pd vs clock frequency - 40 - pf clock clock frequency (note 6) dc 2000 1200 khz notes: 3. tested in 4 1 / 2 digit (20.000 count) circuit shown in figure 3. (clock frequen cy 120khz.) 4. tested with a low dielectric absorption integrating capacitor , the 27 ? int out resistor shorted, and r lnt = 0. see component value selection discussion. 5. the temperature range can be extended to +70 o c and beyond as long as the auto-zero and reference capacitors are increased to absorb the higher leakage of the icl7135. 6. this specification relates to the clock frequency range over which the lcl7135 will correctly perform its various functions see max clock frequency section for limitations on the clock frequency range in a syste m. 7. parameter guaranteed by design or characterization. not produ ction tested.
icl7135 fn3093 rev.4.00 page 4 of 15 aug 28, 2007 figure 1. icl7135 test circuit figure 2. icl7135 digital logic inp ut figure 3. analog section of icl7135 28 27 26 25 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 24 set v ref = 1.000v v ref in signal -5v +5v 100k ? 27 ? 100k ? 100k analog gnd input 1 ? f 0.47 ? f 1 ? f 0.1 ? f 100k ? icl7135 0v clock in 120khz underrange overrange strobe run/hold digital gnd polarity clock in busy lsd di d2 d3 d4 msb b8 b4 v- ref analog gnd int out a-z in buf out ref cap 1 ref cap 2 in lo- in hi+ v+ msd d5 lsb b1 b2 v + pad dig gnd c ref+ ref hi in hi int a/z analog az in lo zi c ref buffer common input comparator c az c int r int integrator input v + v - polarity zero- low high crossing detector f/f de(+) de(-) de(-) de(+) az az auto zero int 1 2 3 4 5 611 10 9 87 - + - + + c ref a/z, de( ? ), zi int
icl7135 fn3093 rev.4.00 page 5 of 15 aug 28, 2007 detailed description analog section figure 3 shows the bl ock diagram of the analog section for the icl7135. each measuremen t cycle is divided into four phases. they are (1) auto-zero (az), (2) signal-integrate (int) , (3) de-integrate (de) and ( 4) zero-integrator (zl). auto-zero phase during auto-zero, three things h appen. first, input high and lo w are disconnected from the pins and internally shorted to analog common. second, the reference capacitor is charged to the reference voltage. third, a fe edback loop is closed around the system to charge the auto-zero capacitor c az to compensate for offset voltages in the buffer am plifier, integrator, and compar ator. since the comparator is included in the loop, the az accuracy i s limited only by t he noise of the system. in any case, the offse t referred to the inpu t is less than 10 ? v. signal integrate phase during signal integrate, the aut o-zero loop is opened, the inte rnal short is removed, and the inte rnal input high and low are connected to the external pins. t he converter then integrates t he differential voltage between in hi and in lo for a fixed time. this differential voltage can be wit hin a wide common mode range; within one volt of either supply . if, on the other hand, the in put signal has no return with respect to the converter power supply , in lo can be tied to analog common to establish the correct common-mode voltage. at the end o f this phase, the polarity of the integrated signal is la tched into the polarity f/f. de-integrate phase the third phase is de-integrate or reference integrate. input low is internally connected to analog common and input high is connected across the previously charged reference capaci- tor. circuitry within the chip ensures that the capacitor will be connected with the correct polar ity to cause the integrator out - put to return to zero. the time required for the output to retu rn to zero is proportional to the input signal. specifically the d igital reading displayed is: . zero integrator phase the final phase is zero integrat or. first, input low is shorted to analog common. second, a fee dback loop is closed around the system to inpu t high to cause the inte grator output to retu rn to zero. under normal condition , this phase lasts from 100 to 200 clock pulses, but after an overrange conversion, it is extended to 6200 clock pulses. differential input the input can accept differentia l voltages anywhere within the common mode range of the input amp lifier; or specifically from 0.5v below the positive supply t o 1v above the negative supply. in this range the system has a cmrr of 86db typical. however, since the integrator also swings with the common mode voltage, care must be exercise d to assure the integrator output does not saturate. a worst case conditi on would be a large positive common-mode voltage with a near full scale negative differentia l input voltage. the negative input signal drives the integrator positive when most of its swing has been used up by the positiv e common mode voltage. for thes e critical applications the integrator swing can be reduced to less than the recommended 4v full scale swing with some lo ss of accuracy. the integrator output can swing within 0.3v of either supply without loss of linearity. analog common analog common is used as the input low return during auto- zero and de-integrate. if in lo is different from analog common, a common mode voltage exists in the system and is taken care of by the excellent c mrr of the converter. however, in most applications in lo will be set at a fixed known voltage (power supply common for instance). in this application, analog common should be tied to the same point, thus removing the common mode voltage from the converter. the reference voltage is referenced to analog common. reference the reference input m ust be generated as a positive voltage with respect to common, a s shown in figure 4. output count 10,000 v in v ref --------------- ?? ?? ?? = figure 4a. figure 4b. figure 4. using an external reference i z 6.8v v- zener ref hi icl7135 common v+ 6.8k ? icl8069 ref hi icl7135 common v+ v+ 20k ? 1.2v reference
icl7135 fn3093 rev.4.00 page 6 of 15 aug 28, 2007 digital section figure 5 shows the digital s ection of the icl7135. the icl7135 includes several pins which allow it to operate conveniently in more sophist icated systems. these include: run/hold (pin 25) when high (or open) the a/d wil l free-run with equally spaced measurement cycles every 40,00 2 clock pulses. if taken low, the converter will continue the full measuremen t cycle that it is doing and then hold this reading as long as r/h is held low. a short positive pulse (greater than 300ns) will now initiate a n ew measurement cycle, beginni ng with between 1 and 10,001 counts of auto zero. if the pulse occurs before the full measurement cycle (40,002 counts ) is completed, it will not be recognized and the converte r will simply complete the measurement it is doing. an ex ternal indication that a full measurement cycle has been comple ted is that the first strobe pulse (see below) will occur 101 counts after the end of this cycle. thus, if run/hold is low and has been low for at least 101 counts, the converter is hol ding and ready to start a new measurement wh en pulsed high. strobe (pin 26) this is a negative goi ng output pulse that aids in transferring the bcd data to exter nal latches, uarts, or microprocessors. there are 5 negat ive going strobe pulses that occur in the center of each of the digit drive pulses and occur once and onl y once for each measurement cycle starting 101 clock pulses after the end of the full measu rement cycle. digit 5 (msd) goes high at the end of the measurem ent cycle and stays on for 201 counts. in the center of this digit pulse (to avoid race condit ions between changing bcd and digi t drives) the first strobe pulse goes negative for 1 / 2 clock pulse width. similarly, after digit 5, digit 4 goes high (fo r 200 clock pulses) and 100 pulse s later the strobe goes negative for t he second time. this continues through digit 1 (ls d) when the fifth and last strobe pulse is sent. the digit drive will continue to scan (unless the previous signal wa s overrange) but no additional strobe pulses will be sent unt il a new measurement is available. busy (pin 21) busy goes high at the beginning of signal integrate and stays high until the first clock pulse a fter zero crossing (or after end of measurement i n the case of an overra nge). the internal latches are enabled (i.e., loaded ) during the first clock pulse after busy and are latched at t he end of this clock pulse. the circuit automatically reverts to auto-zero when not busy, so it may also be consi dered a (zl + az ) signal. a very simple means for transmitting the data down a single wire pair from a remote location would be to and busy with clock and subtract 10,001 count s from the number of pulses received - as mentioned previously there is one no-count pulse in each reference integrate cycle. overrange (pin 27) this pin goes positive when the input signal exceeds the range (20,000) of the conver ter. the output f/f is set at the end of busy and is reset to zero at t he beginning of reference integrate in the next measurement cycle. underrange (pin 28) this pin goes positive when the reading is 9% of range or less. the output f/f is set at the end of busy (if the new reading is 1800 or less) and is reset at the beginning of signal integrate of the next reading. polarlty (pin 23) this pin is positive for a positive input signal. it is valid e ven for a zero reading. in other words, +0000 means the signal is positive but less than the least significant bit. the converter can be used as a null detector by forcing equal frequency of (+ ) and (-) readings. the null at t his point should be less than 0. 1 lsb. this output becomes valid at the beginning of reference integrate and remains correct until it is revalid ated for the n ext measurement. v + polarity digital clock run/ busy over strobe under multiplexer analog gnd in hold range range section msb lsb control logic counters zero cross. det. polarity ff latch latch latch latch latch 11 23 12 17 18 19 20 24 22 27 25 28 26 21 13 14 15 16 d1 d2 d3 d4 b1 b2 b4 b8 d5 figure 5. digital section of the icl7135
icl7135 fn3093 rev.4.00 page 7 of 15 aug 28, 2007 digit drives (pins 12 , 17, 18, 19 and 20) each digit drive is a positive going signal that lasts for 200 clock pulses. the scan sequence is d5 (msd), d4, d3, d2, and d1 (lsd). all five digits are scanned and this scan is continuous unless an overrange occurs. then all digit drives are blanked f rom the end of the strobe sequence unt il the beginning of reference integrate when d5 will start t he scan again. this can give a blinking display as a vis ual indication of overrange. bcd (pins 13, 14, 15 and 16) the binary coded decimal bits b8, b4, b2, and b1 are positive logic signals that go on simultaneously with the digit driver signal. component value selection for optimum performance of the analog section, care must be taken in the selection of values for the integrator capacitor a nd resistor, auto-zero capacit or, reference voltage, and conversion rate. these values must be chosen to suit the particular application. integrating resistor the integrating resist or is determined by the full scale input voltage and the output current of the buffer used to charge the integrator capacitor. both the buffer amplifier and the integra tor have a class a out put stage with 100 ? a of quiescent current. they can supply 20 ? a of drive current with negligible non- linearity. values of 5 ? a to 40 ? a give good results, with a nominal of 20 ? a, and the exact value o f integrating resistor may be chosen by: . integrating capacitor the product of integrating resi stor and capacitor should be selected to give the maximum voltage swing which ensures that the tolerance built-up will not saturate the integrator sw ing (approx. 0.3v from either supply). for ? 5v supplies and analog common tied to supply ground, a ? 3.5v to ? 4v full scale integrator swing is fine, and 0.47 ? f is nominal. in general, the value of c lnt is given by: , . a very important characteristic o f the integrating capacitor is that it has low dielectric absor ption to prevent roll-over or ratiometric errors. a good test for dielectric absorption is to use the capacitor with the inpu t tied to the reference. this ratiometric condition sho uld read half scale 0.9999, and any deviation is probably due to dielectric absorption. polypropylene capacitors give undetectable errors at reasonable cost. polystyrene and polycarbonate capacitors may also be used in less critical applications. auto-zero and reference capacitor the physical size of the auto-ze ro capacitor has an influence on the noise of the system. a larger cap acitor value reduces system noise. a larger physical size increases system noise. the reference capacitor should be large enough such that stray capacitance to ground from its nodes is negligible. the dielectric absorption of t he reference cap and auto-zero cap are only import ant at power-on or whe n the circuit is recovering from an overload. thus, smaller or cheaper caps can be used here if accurate readings are not required for the first few seconds of recovery. reference voltage the analog input required to generate a full scale output is v ln = 2v ref . the stability of the re ference voltage is a major factor in the overall absolute accuracy of the converter. for this reason, it is recommended that a high qualit y reference be used where high-accuracy absolute measurements are being made. rollover resistor and diode a small rollover error occurs i n the icl7135, but this can be easily corrected by adding a d iode and resistor in series between the integrator out put and analog common or ground. the value shown in the sch ematics is optimum for the recommended conditions, but i f integrator swing or clock frequency is modified, adjustment may be needed. the diode can be any silicon diode such as 1n914. these components can be eliminated if rollover erro r is not important and may be altered in value to correct other (small) sources of rollover a s needed. max clock frequency the maximum conversion rat e of most dual-slope a/d converters is limited by the frequency response of the comparator. the comparator in this circuit follows the integrat or ramp with a 3 ? s delay, and at a clock frequency of 160khz (6 ? s period) half of the first reference i ntegrate clock period is lost in delay. this means that the meter read ing will change from 0 to 1 with a 50 ? v input, 1 to 2 with a 150 ? v input, 2 to 3 with a 250 ? v input, etc. this transition at mid-point is considered desirable by most u sers; however, if the clock frequency is increased appreciably above 160khz, the instrument will flash 1 on noise peaks even when the input is shorted. for many dedicated applicati ons where the input signal is always of one polarity, the delay of the comparator need not be a limitation. since the non-lin earity and noise do not increase substantially with frequency, clo ck rates of up to ~1mhz may be used. for a fixed clock frequency, the extra count or counts caused by comparator delay w ill be constant and can be subtracted out digitally. the clock frequency may be extended above 1 60khz without this error, however, by using a l ow value resistor in series wi th r int full scale voltage 20 ? a ------------------------------------------- - = ? i int ? integrator output voltage swing --------------------------------------------------------------- ------------------ - ?? ?? ?? = ? a) integrator output voltage swing --------------------------------------------------------------- ------------------ =
icl7135 fn3093 rev.4.00 page 8 of 15 aug 28, 2007 the integrating capacitor. the effect of the resistor is to introduce a small pedestal voltage on to the integrator output at the beginning of the r eference integrate phase. by careful selection of the ratio between this resisto r and the integratin g resistor (a few tens of ohms in the recommended circuit), the comparator delay can be co mpensated and the maximum clock frequency extended by appro ximately a factor of 3. at higher frequencies, ringing and second order breaks will cause significant non-linearities in the first few counts of the instrument. see application note an017. the minimum clock frequency is established by leakage on the auto-zero and reference caps. with most devices, measurement cycles as long as 10s give no measurable leakage error. to achieve maximum rejection of 60hz pickup, the signal integrate cycle should be a mu ltiple of 60hz. oscillator frequencies of 300khz, 200k hz, 150khz, 120khz, 100khz, 40khz, 33 1 / 3 khz, etc. should b e selected. for 50hz rejection, oscillator frequencies of 250khz, 166 2 / 3 khz, 125khz, 100khz, etc. would be suitable. note t hat 100khz (2.5 readings/sec) wil l reject both 50hz and 60hz. the clock used should be free from significant phase or frequency jitter. several suitable low-cost oscillators are sho wn in the typical applications sec tion. the multiplexed output means that if the display takes significant current from the lo gic supply, the clock s hould have good psrr. zero-crossing flip-flop the flip-flop interrogates the data once every clock pulse afte r the transients of the previous clock pulse and half-clock pulse have died down. false zero-cro ssings caused by clock pulses are not recognized. of course , the flip-flop delays the true zero-crossing by up to one count in ever y instance, and if a correction were not made, the display would always be one count too high. therefore, the counter is disabled for one cloc k pulse at the beginnin g of phase 3. this one-count delay compensates for the delay of t he zero-crossing flip-flop, and allows the correct n umber to be latched into the display. similarly, a one-count delay at the beginning of phase 1 gives an overload display of 0000 in stead of 0001. no delay occurs during phase 2, so that true ra tiometric readings result. evaluating the error sources errors from the ideal cycle are caused by: 1. capacitor droop due to leakage. 2. capacitor voltage change due to charge suck-out (the reverse of charge injection) when the switches turn off. 3. non-linearity of buffer and integrator. 4. high-frequency limitations of buffer, integrator, and comparator. 5. integrating capacitor non-lin earity (dielectric absorption). 6. charge lost by c ref in charging c stray . 7. charge lost by c az and c lnt to charge c stray . each error is analyzed for its error contribution to the conver ter in application notes listed on the back page, specifically application note an017 and application note an032. noise the peak-to-peak noise around zero is approximately 15 ? v (peak-to-peak value not exceeded 95% of the time). near full scale, this value increases to approximately 30 ? v. much of the noise originates in the auto-zero loop, and is proportional to the ratio of the input signal to the reference. analog and digital grounds extreme care must be taken to avoid ground loops in the layout of icl7135 circuits, especially in high-sensitivity circuits. i t is most important that return currents from digital loads are not fed into the ana log ground line. d5 d4 d3 d2 d1 digit scan expanded scale ? first d5 of az and 1000 ? / strobe reference under-range integrator busy auto for over-range signal integrate integrate ref int one count longer below when applicable over-range when applicable output zero 10,001/ counts signal int. 10,000/ counts reference integrate 20,001/ counts max. counts d5 d4 d3 d2 d1 auto zero full measurement cycle 40,002 counts digit scan for over-range figure 6. timing diagram for outputs
icl7135 fn3093 rev.4.00 page 9 of 15 aug 28, 2007 power supplies the icl7135 is designed to work from ? 5v supplies. however, in selected applications no n egative supply is required. the conditions to use a single +5v supply are: 1. the input signal can be referenced to the center of the common mode range of the converter. 2. the signal is less than ? 1.5v. see differential in put for a discussion o f the effects this w ill have on the integrator swin g without loss of linearity. typical applications the circuits which follow show some of the wide variety of possibilities and serve to illust rate the exceptional versatili ty of this a/d converter. figure 7 shows the comp lete circuit for a 4 1 / 2 digit ( ? 2.000v) full scale) a/d with led readout using the icl8069 as a 1.2v temperature compensa ted voltage reference. it uses the band- gap principal to achieve excell ent stability and low noise at reverse currents down to 50 ? a. the circuit also shows a typical r-c input filter. depending on the applica tion, the time- constant of this filter can be made faster, slower, or the filt er deleted completely. the 1 / 2 digit led is driven from the 7 segment decoder, with a zero reading blanked by connecting a d5 signal to rbl input of the decoder. the 2-gate clock circuit should use cmos gates to maintain good power supply rejection. a suitable circuit for driving a plasma-type display is shown i n figure 8. the high voltage ano de driver buffer is made by dionics. the 3 and gates and caps driving bi are needed for interdigit blanking of multiple-digit display elements, and can be omitted if not needed. the 2.5k ?? and 3k ? resistors set the current levels in the display . a similar arrangement can be used with nixie ? tubes. the popular lcd displays can be interfaced to t he outputs of the icl7135 with suitable disp lay drivers, such as the icm7211a as shown in figur e 9. a standard cmos 4030 quad xor gate is used for displaying the 1 / 2 digit, the polarity, and an overrange fla g. a similar circ uit can be use d with the icl7212a led drive r and the icm7235a vacuum fluorescent driver with appropri ate arrangements made for the extra outputs. of course, anothe r full driver circuit could b e ganged to the one shown if requi red. this would be useful if additional annunciators were needed. the figure shows the complete circuit for a 4 1 / 2 digit ( ? 2.000v) a/d. figure 10 shows a more complic ated circuit for driving lcd displays. here the data is la tched into the icm7211 by the strobe signal and overrange is indicated by blanking the 4 full digits. figure 7. 4 1 / 2 digit a/d converter with a mul tiplexed common anode led displa y analog gnd 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +5v 6.8k ? v ref = signal 0.1 ? f -5v icl8069 1 2 5 b1 b a 7447 3 4 b2 c d e f g b4 b8 c rc network ? osc = 0.45/rc 1.000v 10k ? 100k ? 27 ? 47k 150 ? input 1 ? f r rbi 100k ? +5v 100k 1 ? f 0.47 ? f 21 150 ? 150 ? 4.7k +5v icl7135 v- ref analog int out az in buf out rc1 rc2 input lo input hi v+ d5 b1 b2 ur or strobe r/h dig. gnd pol clock busy d1 d2 d3 d4 b8 b4 common (note 1) note: 1. for finer resolution on scale factor adjust, use a 10 turn po t or a small pot in series with a fixed resistor.
icl7135 fn3093 rev.4.00 page 10 of 15 aug 28, 2007 a problem sometimes encounter ed with both led and plasma- type display driving is that of clock source sup ply line variat ions. since the supply is shared with the display, any variation in voltage due to the display reading may cause clock supply volta ge modulation. when in overrange t he display alternates between a blank display and the 0000 overrange indication. this shift occ urs during the reference integrate phase of conversi on causing a lo w display reading just after ove rrange recovery. both of the abov e circuits have considerable current flowing in the digital suppl y from drivers, etc. a clock source using an lm311 voltage comparator with positive feedback (figure 11) could minimize any clock frequency shift problem. the icl7135 is designed to work from ? 5v supplies. however, if a negative supply is not ava ilable, it can be generated with an icl7660 and two capacitors (figure 12). interfacing with uarts and microprocessors figure 13 shows a very simple int erface between a free-running icl7135 and a uart. the five strobe pulses start the transmission of the five data words. the digit 5 word is 0000xxxx, digit 4 is 1000xxxx, digit 3 is 0100xxxx, etc. also the polarity is transmitted indire ctly by using it to drive the even parity enable pin (epe). if epe of the receiver is held low, a parity flag at the receiver can be decoded as a positive signal, no fl ag as negative. a complex arrangement i s shown in figure 14. here the uart can instruct the a/d to b egin a measurement sequence by a word on rrl. the busy signal resets the data ready reset (drr). again strobe starts the transmit sequence. a quad 2 input multiplexer is used to superimpose polarity, over-range, and under-range onto the d5 word since in this instance it is known that b2 = b4 = b8 = 0. for correct operation it is important that t he uart clock be fa st enough that each word is transmi tted before the next strobe pulse arrives. parity is locked into the uart at load time but does not change in this connecti on during an output stream. circuits to interface the icl7135 directl y with three popular microprocessors are shown in figure 15 and figure 16. the 8080/8048 and the mc680 0 groups with 8-bit buses need to have polarity, over-range and under-range multiplexed onto the digit 5 sword - as in the uar t circuit. in each case the microprocessor can instru ct the a/d when to begin a measurement and when to hold this measurement. application notes figure 8. icl7135 plasma display circuit figure 9. lcd display with digit blanking on overrange b1 47k 0.02 ? f a g d b8 d1 2.5k dm rbi 8880 hi voltage buffer d1 505 icl7135 5k +5v pol d5 rb0 a a g 0.02 ? f pol gates 0v prog are 7409 +5 3k v + +5 0v bi 0.02 ? f 0.02 ? f 0.02 ? f v+ dgnd 28 b1 26 strobe 14 b2 13 b1 12 d5 27 or cd4011 +5v 1 / 4 cd4030 icl7135 icm7211a 15 b4 16 b8 17 d4 19 d2 20 d1 23 pol cd4081 cd4071 27 b0 29 b2 34 d4 33 d3 30 b3 32 d2 5 bp 31 d1 18 d3 +5v bp 1 / 2 cd4030 4 1 / 2 digit lcd display 1/4 cd4030 note # description an016 selecting a/d converters an017 the integrating a/d converter an018 dos and donts of applying a/d converters an023 low cost digital panel meter designs an028 building an auto-ranging dmm using the 8052a/7103a a/d converter pair an054 display driver family combines convenience of use with microprocessor interfaceability an9510 basic analog for digital designers an9609 overcoming common mode range issues when using intersil integrating converters
icl7135 fn3093 rev.4.00 page 11 of 15 aug 28, 2007 figure 10. driving lcd displays figure 11. lm311 clock source figure 12. generating a negative sup ply from +5v 20 28 27 26 25 24 23 22 21 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ref -5v analog 27 ? 0.47 ? f 1 ? f 100k ? input +5v icl7135 cd4054a 120kc = 3 readings/sec clock in backplane 4 1 / 2 digit lcd display 28 segments d1-d4 optional 2,3,4 icm7211a 300pf 0v 22-100pf voltage gnd capacitor 6-26 v- ref analog int out az in buf out rc1 rc2 input lo input hi v+ d5 b1 b2 37-40 osc 36 v+ 1 ur or strobe r/h dig. gnd pol clock busy d1 d2 d3 d4 b8 b4 1 31 d1 32 d2 33 d3 34 d4 30 b3 29 b2 28 b1 27 b0 35 v- 16 15 14 12 5 3 4 78131110926 +5v +5v +5v 0.1 ? f 1 ? f 100k ? common 5bp 100k ? ? f 16k ? 56k ? +5v 1k ? 30k ? 390pf 1 3 4 8 7 16k ? lm311 + 2 - 1 2 3 4 7 6 5 8 10 ? f - + +5v v out = -5v icl7660 10 ? f - +
icl7135 fn3093 rev.4.00 page 12 of 15 aug 28, 2007 figure 13. icl7135 to uart interface figure 14. complex icl7135 to uart interface figure 15. icl7135 to mc6800, mcs650x interfaced figure 16. icl713 5 to mcs-48, -80, -85 interface epe pol d5 icl7135 nc run/hold strobe tbr tbrl +5v d4 d3 d2 d1 b1 b2 b4 tro b8 123456 8 7 uart serial output to receiving uart im6402/3 1a 2a 3a b4 b2 b1 1b 2b 3b 234 d2 d3 d5 8 7 6 d1 5 1y 2y 3y 1 b8 pol over under select run/hold strobe busy icl7135 enable im6402/3 tro rri drr dr tbrl epe +5v 100pf 10k 74c157 tbr d4 en 74c157 1b 2b 3b 1a 2a 3a 1y 2y 3y b1 d5 b8 b4 b2 d1 d2 d3 d4 icl7135 1y pa0 pa1 pa2 pa4 pa5 pa6 pa7 pol over under select run/ hold strobe ca1 ca2 mc6820 mc680x or mcs650x pa3 en 74c157 1b 2b 3b 1a 2a 3a 1y 2y 3y b1 d5 b8 b4 b2 d1 d2 d3 d4 icl7135 1y pa0 pa1 pa2 pa4 pa5 pa6 pa7 pol over under select run/ hold strobe stb a pb0 8255 (mode1) 80c48 8080 8085, etc. pa3
icl7135 fn3093 rev.4.00 page 13 of 15 aug 28, 2007 typical integrator amplifier output waveform (int pin) design information summary sheet ? clock input the icl7135 does no t have an internal oscillator. it requires an external clock. f clock (typ) = 120khz ? clock period t clock = 1/f clock ? integration period t int = 10,000 x t clock ? 60/50hz rejection criterion t int /t 60hz or t int /t 50hz = integer ? optimum integration current i int = 20 ? a ? full-scale analog input voltage v lnfs (typ) = 200mv or 2v ? integrate resistor ? integrate capacitor ? integrator output voltage swing ?v int maximum swing: (v- + 0.5) < v int < (v+ - 0.5v) v int typically = 2.7v ? display count ? conversion cycle t cyc = t cl0ck x 40002 when f clock = 120khz, t cyc = 333ms ? common mode input voltage (v- + 1v) < v ln < (v+ - 0.5v) ? auto-zero capacitor 0.01 ? f < c az < 1 ? f ? reference capacitor 0.1 ? f < c ref < 1 ? f ? power supply: dual ? 5v v+ = +5v to gnd v- = -5v to gnd ? output type 4 bcd nibbles with pola rity and overrange bits there is no internal referenc e available on the icl7135. an external reference is requ ired due to the icl7135s 4 1 / 2 digit resolution. r int v infs i int ---------------- - = ?? i int ?? v int ------------------------------- - = ?? i int ?? c int ------------------------------- - = ? v in v ref ---------------- - ? = auto zero phase (counts) 30001 - 10001 integrate phase fixed 10000 counts de-integrate phase 1 - 20001 counts total conversion time = 40002 x t clock
icl7135 fn3093 rev.4.00 page 14 of 15 aug 28, 2007 die characteristics die dimensions: (120 mils x 130 mils) x 525 ? m ? 25 ? m metallization: type: al thickness: 10k ? ? 1k ? passivation: type: nitride/silox sandwich thickness: 8 k nitride over 7k silox metallization mask layout icl7135 v+ in hi in lo ref ref cap+ cap+ buff out az in int out analog common reference v- underrange overrange strobe r/h digital pol clock in gnd busy (lsd)d1 d2 (msd) d5 (lsb) b1 b2 b4 (msb) b8 d4 d3
fn3093 rev.4.00 page 15 of 15 aug 28, 2007 icl7135 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2000-2007. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between eng lish and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the mo series symbol list in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are m easured with the package seated i n jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrus ions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendic- ular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not i nclude dambar protrusions. damb ar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1. 14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e28.6 (jedec ms-011-ab issue b) 28 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.250 - 6.35 4 a1 0.015 - 0.39 - 4 a2 0.125 0.195 3.18 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.030 0.070 0.77 1.77 8 c 0.008 0.015 0.204 0.381 - d 1.380 1.565 35.1 39.7 5 d1 0.005 - 0.13 - 5 e 0.600 0.625 15.24 15.87 6 e1 0.485 0.580 12.32 14.73 5 e 0.100 bsc 2.54 bsc - e a 0.600 bsc 15.24 bsc 6 e b - 0.700 - 17.78 7 l 0.115 0.200 2.93 5.08 4 n28 289 rev. 1 12/00

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